Caching schemes are employed by computer designers to reduce access times by a processor to main memory, and hence, increase system performance. In many computing systems, main memory consists of a large array of memory devices with speeds which are slow relative to processor speeds. During accesses to main memory, the processor is forced to insert additional wait states to accommodate the slower memory devices. System performance during memory accesses can be enhanced with a high performance cache memory. Smaller in size than main memory and significantly faster, the cache memory provides fast local storage for data and instruction code which is frequently used by the processor. In computing systems with caches, memory operations by the processor are first transacted with the cache. The slower main memory is only accessed by the processor if the memory operation cannot be completed with the cache. In general, the processor has a high probability of fulfilling a majority of its memory operations with the cache. Consequently in computing systems which employ a cache memory, effective memory access times between a processor and relatively slow main memory can be reduced.
Shown in FIG. 1 is an example of a prior art data processing system 10 comprised of a processor 11, a cache 12, a cache controller 13, a main memory 14, and address bus 15, and a data bus 16. The cache 12 may be highly optimized according to a number of different features. One important feature which affects cache performance and design complexity is the handling of writes by the processor 11 or an alternate bus master (not shown). Since two copies of a particular piece of data or instruction code can exist, one in main memory 14 and a duplicate in the cache 12, writes to either main memory 14 or the cache 12 can result in incoherency between the two storage systems. Incoherency between the cache 12 and main memory 14 during processor writes is handled using two techniques. A first technique guarantees consistency between the cache 12 and main memory 14 by writing to both the cache 12 and the main memory 14 during processor writes ("write-through"). A second technique handles processor writes by writing only to the cache 12, and designating the cache entries which have been altered by the processor 11 ("write-back"). In some caching schemes it may be desirable to delay the performance of the memory write, pending a determination of whether a cache "hit" or "miss" occurred. A co-pending application entitled "Cache Memory With Write Enable" Ser. No. 07/509,527, by Richard Crisp et al, and assigned to the assignee hereof, discloses a cache memory with a write enable feature which allows the user to delay the write until the cache controller determines whether a cache "hit" or "miss" occurred.
The data processing system's ability to expeditiously handle write requests from the processor is often dependent upon the performance of the fast static random access memories (FSRAMs) used for the cache. Thus, FSRAM designs which provide features to support cache functionality may significantly enhance overall systems performance. For example, many of today's high performance data processing systems rapidly transmit data between the memory system, and the processor using a global data bus. Typically, these high performance systems rely upon some type of error checking scheme (i.e. parity, error correction code (ECC)) to insure the integrity of the data transferred. Typically, the size of the memory arrays used in cache memory does not warrant the complexity of ECC as an approach to error checking. Generally, simple parity checking provides the most cost efficient scheme for error checking.
In complex 32-bit data processing systems, parity checking is performed on a byte basis, therefore, necessitating the use of four (4) parity bits (one parity bit per byte of data). Typically, cache memory systems designed to support byte parity rely upon a unique memory device (i.e. FSRAM) to provide and store each parity bit. Thus, four (4) memory devices are required to support byte parity in a 32-bit data processing system. The use of four (4) memory devices to provide parity checking may degrade the overall system performance due to additional timing constraints. Furthermore, the loading on the control signals caused by four (4) memory devices, coupled with the additional power consumption attributable to the operation of the cache memory system, may also result in system performance degradation. Thus, it is desirable to provide a cache memory system capable of overcoming the foregoing problems.